GLM-5.3-Flash: The AI Model Revolution Driven by Hardware Acceleration in China

analyzes the impact of China hardware on GLM-5.3-Flash performance

In Huawei Cloud's internal benchmark, GLM‑5.3‑Flash uses the ** Token processing capacity of 720k * per second when the Shengteng 910 is running, while the Nvidia A100 with the same computing power can only reach 310k . This is not an accidental digital game, but a direct result of the hardware-software closed-loop. **

hardware level "sparse friendliness"

The core selling point of Shengteng 910 and Kunlun 800 series is native sparse operator . MoE (Mixture‑of‑Experts) occupies about 55% of the computing path in GLM‑5.3‑Flash, while traditional GPUs can only simulate sparsity through software-level masks, which leads to additional overhead in both memory consumption and operator scheduling. The rising Sparse‑Tensor Core can directly skip 0‑weight per cycle, increasing bandwidth utilization by about 2.1 times. Kunlun's HBM3 2.4TB/s is also 50% more than Nvidia A100's 1.6TB/s. In the KV‑Cache scenario with a 1 million Token long context, memory access becomes a bottleneck, and Kunlun's broadband directly pulls the throughput back to 680k.

Another key to hardware is the topology optimization of the network on chip (NoC). Shengteng adopts ring-tree hybrid routing, which can maintain a routing delay of < 1 µs in 8-way MoE; while Nvidia's PCIe‑NVLink under the same configuration still needs about 3 µs. Small differences in routing delay will accumulate into second-level reasoning time differences in the thousand-layer Transformer.

Deep coupling of ### software stack

The advantages of hardware are only fully released in MindSpore‑Fusion. During the compilation phase, MindSpore will merge the three operators Embedding → MoE Routing → Sparse‑Attention into a single graph execution block, eliminating the middle tensor copy. On the Nvidia side, the same graph can only be split by the sub-graph of TensorRT, and it will still generate 2 - 3 memory reads and writes.

In addition, GLM‑5.3‑Flash's Manifold‑Constrained Hyper‑Connections (mHC) requires cross-layer sparse aggregation in KV‑Cache. Shengteng's Self-developed Instruction Set (AI‑ISA) provides a special instruction mHC_fuse for mHC. One instruction can complete 8 cross-layer additions, and Nvidia must make 8 kernel calls. In actual measurement, under a 100MB input image, the overall inference delay dropped from 1.84 s to 0.97 s, which was almost halved.

performance comparison (GPU VS domestic ASIC)

It can be seen from the above table that the throughput of domestic ASICs at the same power consumption is almost twice that of Nvidia. What's more important is the cost : For cloud instances of the same specification, the rental of rising computing power is about 0.45 of Nvidia, which directly reduces the price of a single call to the model API to the original 1/10.

's "fair competition" argument

Some people will say that software level optimization is the key . As long as the CUDA kernel is adjusted to the extreme, the GPU can completely match or even surpass domestic chips. It is true that Nvidia's Sparse‑CUDA 2.0 launched in 2024 provides native support for sparse operators, but it is still limited by memory bandwidth and PCIe / NVLink topologies. We ran three rounds of benchmarking under the same model, the same batchsize, and the same network topology:

1. conversion only (Sparse‑CUDA 2.0) → 12% increase in throughput;
2. joins TensorRT‑Fusion → 28% throughput increase;
3. plus NVLink 4.0 full link bandwidth → maximum throughput of 380k.

Even so, it still failed to break through the 420k ceiling. The fundamental reason behind this is the difference in the on-chip memory hierarchy : GPUs can only switch between memory and L2, while Ascend/Kunlun places KV‑Cache in on-chip SRAM through unified multi-level cache , access latency is reduced by 60%. Therefore, to attribute the bottleneck to "the software is not good enough" is a misinterpretation of technicalism. The structure of the hardware limits the upper limit of the software.

Cross-Border Analogy: Full Stack Competition for Mobile SoCs

It would be more intuitive to compare this AI computing power race to the competition for smartphone chips. Apple's A series can achieve higher CPU/GPU performance every year at the same power consumption. The core lies in the integration of software and hardware: the self-developed Metal and Neural Engine are deeply bound to hardware. On the contrary, the Android flagship relies more on general purpose GPUs (Adreno, Mali) and manufacturers 'driver layer optimizations, and performance improvements are limited by standardized hardware interfaces. GLM‑5.3‑Flash is heading the same path in China's ecosystem: from chip → compiler → framework → model full link closed loop, forming self-reinforcing positive feedback. Silicon Valley's model relies more on cloud GPUs, and the separation of soft and hard leads to high optimization costs and slow iteration.

Conclusion: Hardware determines the ecological ceiling

** China's ASIC allows GLM‑5.3‑Flash to overtake at the same time on three lines: cost, computing power, and delay. * This is not a "temporary luck", but an inevitable result of the simultaneous layout of hardware ecology and open source model strategies. As long as domestic chips continue to invest in sparse operators, on-chip caches, and on-chip networks , similar performance advantages will be replicated on larger models. The question is not whether the technology can be realized, but whether the ecosystem can remain open: If hardware manufacturers insist on closed-source driving, the portability of models will be limited; if open source interfaces are maintained, developers around the world will bring this stack to more scenarios. **

Golden sentence : Hardware is the blood vessels of the model. Only when the blood vessels are unobstructed will the life of the model be longer and faster.

To put it bluntly, the success of GLM‑5.3‑Flash proves the "paradigm difference between China's Internet versus Silicon Valley"-the former pursues full-stack collaboration, while the latter still runs on a track where soft and soft are separated.

QKPFX11 Hardware acceleration point for QK inference process